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CY7C1046D
4-Mbit (1 M x 4) Static RAM
4-Mbit (1 M x 4) Static RAM
Features

Functional Description
The CY7C1046D[1] is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1046D is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout.
Pin- and function-compatible with CY7C1046B High speed tAA = 10 ns CMOS for optimum speed/power Low active power ICC = 90 mA @ 10 ns Low CMOS Standby Power ISB2 = 10 mA Data Retention at 2.0 V Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in lead-free 400-mil-wide 32-pin SOJ package

Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
INPUT BUFFER
ROW DECODER
I/O0
SENSE AMPS 1M x 4
I/O1 I/O2 I/O3
CE WE OE
COLUMN DECODER
POWER DOWN
Note 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document Number: 38-05705 Rev. *D
*
198 Champion Court
A 11 A 12 A 13 A14 A15 A16 A17 A18 A19
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 1, 2010
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CY7C1046D
Contents
Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 8 Read Cycle No. 1 ........................................................ 8 Read Cycle No. 2 (OE Controlled) .............................. 8 Write Cycle No. 1 (CE Controlled) ............................... 9 Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ...................................................... 9 Write Cycle No. 3 (WE Controlled, OE LOW) ........... 10 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagram ............................................................ 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15
Document Number: 38-05705 Rev. *D
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CY7C1046D
Selection Guide
-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current (mA) 10 90 10 Unit ns mA mA
Pin Configuration
SOJ Top View
A0 A1 A2 A3 A4 CE I/O0 VCC GND I/O1 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O3 GND VCC I/O2 A14 A13 A12 A11 A10 NC
Document Number: 38-05705 Rev. *D
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CY7C1046D
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage on VCC to relative GND[2] .....-0.5 V to +6.0 V DC voltage applied to outputs in high Z state[2] ................................... -0.5 V to VCC + 0.5 V DC input voltage[2] ............................... -0.5 V to VCC + 0.5 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, method 3015) Latch-up current ..................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -40 C to +85 C VCC 4.5 V-5.5 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[2] GND < VI < VCC GND < VOUT < VCC, output disabled VCC = Max, f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 ISB2 Automatic CE Power-Down Current --TTL inputs Automatic CE Power-Down Current --CMOS inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC - 0.3 V, VIN > VCC - 0.3 V, or VIN < 0.3 V, f = 0 Input leakage current Output leakage current VCC operating supply current Test Conditions VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA -10 Min 2.4 - 2.0 -0.5 -1 -1 - - - - - - Max - 0.4 VCC + 0.5 0.8 +1 +1 90 80 70 60 20 10 mA mA Unit V V V V A A mA
Capacitance[3]
Parameter CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max 8 8 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient)[3] Thermal Resistance (Junction to Case)[3] Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board SOJ Package 53.44 38.25 Unit C/W C/W
Notes 2. VIL (min) = -2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05705 Rev. *D
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CY7C1046D
AC Test Loads and Waveforms [4]
Z = 50
OUTPUT 50 1.5 V * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT
3V
ALL INPUT PULSES 90% 10% 90%VCC 10%VCC
30 pF*
GND Rise Time:1 V/ns R1 481
(b)
Fall Time: 1 V/ns
(a)
5V
OUTPUT 5 pF High Z Characteristics: INCLUDING JIG AND SCOPE (c) R2 255
Equivalent to: THEVENIN EQUIVALENT 167 1.73 V OUTPUT
Note 4. AC characteristics (except high Z) are tested using the load conditions shown in (a). High Z characteristics are tested for all speeds using the test load shown in (c).
Document Number: 38-05705 Rev. *D
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CY7C1046D
Switching Characteristics[5]
Over the Operating Range Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write cycle time CE LOW to write end Address set-up to write end Address hold from write end Address set-up to write start WE pulse width Data set-up to write end Data hold from write end WE HIGH to low WE LOW to high Z[8] Z[7, 8] 10 7 7 0 0 7 6 0 3 - - - - - - - - - - 5 ns ns ns ns ns ns ns ns ns ns VCC(typical) to the first access[6] Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low CE LOW to low Z[8] Z[8] OE HIGH to high Z[7, 8] CE HIGH to high Z[7, 8] CE LOW to power-up CE HIGH to power-down 100 10 - 3 - - 0 - 3 - 0 - - - 10 - 10 5 - 5 - 5 - 10 s ns ns ns ns ns ns ns ns ns ns ns Description 7C1046D-10 Min Max Unit
Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads.Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05705 Rev. *D
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CY7C1046D
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR[12] tR
[13]
Description VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time
Conditions[11] VCC = VDR = 2.0 V, CE > VCC - 0.3 V, VIN > VCC - 0.3 V or VIN < 0.3 V
Min 2.0 - 0 tRC
Max - 10 - -
Unit V mA ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE 4.5 V tCDR VDR > 2 V 4.5 V tR
Notes 11. No inputs may exceed VCC + 0.3 V. 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 38-05705 Rev. *D
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CY7C1046D
Switching Waveforms
Read Cycle No. 1[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS tRC CE
tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Notes 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05705 Rev. *D
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CY7C1046D
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[17, 18]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 38-05705 Rev. *D
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CY7C1046D
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[20]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 21 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Truth Table
CE H L L L OE X L X H WE X H L H I/O0-I/O3 High Z Data Out Data In High Z Power-down Read Write Selected, outputs disabled Mode Active (ICC) Active (ICC) Active (ICC) Power Standby (ISB)
Notes 20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 21. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 38-05705 Rev. *D
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CY7C1046D
Ordering Information
Speed (ns) 10 Ordering Code CY7C1046D-10VXI Package Diagram 51-85033 Package Type 32-pin (400-Mil) Molded SOJ (Pb-free) Operating Range Industrial
Ordering Code Definitions
CY 7 C 1 04 6 D - 10 VX I Temperature Range: I = Industrial Package Type: VX = 32-pin (400-Mil) Molded SOJ (Pb-free) Speed: 10 ns D = C9, 90 nm Technology 6 = Data width x 4-bits 04 = 4-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress
Please contact your local Cypress sales representative for availability of these parts.
Document Number: 38-05705 Rev. *D
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CY7C1046D
Package Diagram
32-pin (400-Mil) Molded SOJ (51-85033)
51-85033 *C
Document Number: 38-05705 Rev. *D
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CY7C1046D
Acronyms
Acronym CMOS CE I/O OE SRAM TSOP TTL VFBGA WE chip enable input/output output enable static random access memory thin small-outline package transistor-transistor logic very fine-pitch ball grid array write enable Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol ns V s A mA MHz pF C W % nano seconds Volts micro seconds micro Amperes milli Amperes Mega Hertz pico Farad degree Celcius Watts percent Unit of Measure
Document Number: 38-05705 Rev. *D
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CY7C1046D
Document History Page
Document Title: CY7C1046D 4-Mbit (1 M x 4) Static RAM Document Number: 38-05705 REV. ** *A ECN NO. 307613 399070 Issue Date Orig. of Change See ECN See ECN RKF NXR Description of Change New Data Sheet Changed from Advance to Preliminary Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Removed -20 speed bin Removed L-Version Redefined ICC values for Com'l and Ind'l temperature ranges ICC (Com'l): Changed from 70 and 55 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind'l): Changed from 80, 70 and 55 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Added Industrial Operating Range Changed reference voltage level for measurement of Hi-Z parameters from 500 mV to 200 mV Changed VCC to 3 V in the Input pulse waveform at the AC Test Loads and Waveforms on page # 3 Changed tSCE from 8 to 7 ns for -10 speed bin Added Truth Table Added 10 ns parts in the Ordering Information table Changed part names from V33 to V324 in the Ordering Information Table Shaded Ordering Information Table Converted from Preliminary to Final. Removed -12 and -15 Speed bins Removed Commercial Operating Range product information. Changed Maximum Rating for supply voltage from 7V to 6V Changed the Capacitance value of input pins and I/O pins from 6 pF to 8 pF Updated the Thermal Resistance table. Changed tHZWE from 6 ns to 5 ns Added footnote #4 and 11 Updated footnote #7 on High-Z parameter measurement Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table. Added Ordering Code Definitions. Updated Package Diagram. Added Acronyms and Units of Measure. Minor edits and updated in new template.
*B
459072
See ECN
NXR
*C *D
3059162 3098812
10/14/2010 12/01/2010
PRAS PRAS
Document Number: 38-05705 Rev. *D
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CY7C1046D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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(c) Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05705 Rev. *D
Revised December 1, 2010
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